This invention relates to semiconductor memory devices and method of manufacture, and more particularly to a one-transistor dynamic read/write memory cell array.
Dynamic read/write memory cells made by the double-level polysilicon N-channel self-aligned process commonly used in the industry are shown in pending U.S. patent applications Ser. No. 648,594, filed Jan. 12, 1976 and Ser. No. 722,841, filed Sept. 13, 1976, by C-K Kuo now U.S. Pat. No. 4,240,042, both assigned to Texas Instruments, as well as in Electronics, Feb. 19, 1976, pp. 116-121, May 13, 1976, pp. 81-86, and Sept. 28, 1978, pp. 109-116.
Although the double-level polysilicon process has proved to be quite successful and many hundreds of millions of memory devices have been made in this way, there is nevertheless added cost and degradation in yield due to the additional process steps compared to a single level process. Further, the classic cell layout uses a transistor which has a channel length determined by the amount of overlap of the two poly levels, making the characteristics of the transistor difficult to control. Another problem is the necessity of making metal-to-polysilicon contacts to connect the row lines to the gate.
It is the principal object of this invention to provide an improved dynamic read/write memory cell. Another object is to provide a dynamic memory of small cell size. An additional object is to provide a dense array of dynamic memory cells, made by a more efficient method. A further object is to provide an improved way of making dynamic memory cells without using metal-to-polysilicon contacts in the array. Another object is to avoid relying upon alignment precision in defining transistor channel lengths in dynamic memory cells.